Disk drives are a cost effective data storage system for use with a computer or other data processing devices. As shown in FIG. 1, a disk drive 10 comprises a magnetic recording medium, in the form of a disk or platter 12 having a hub 13 and a magnetic read/write transducer 14, commonly referred to as a read/write head. The read/write head 14 is attached to, or formed integrally with, a suspension arm 15 suspended over the disk 12 and affixed to a rotary actuator arm 16. A structural arm 18, fixed to a platform 20 of the disk drive 10, is pivotably connected to the actuator arm 16 at a pivot joint 22. A voice coil motor 24 drives the actuator arm 16 to position the head 14 over a selected position on the disk 12.
As the disk 12 is rotated by a spindle motor (not shown) at an operating speed, the moving air generated by the rotating disk, in conjunction with the physical features of the suspension arm 15, lifts the read/write head 14 away from the platter 12, allowing the head to glide or fly on a cushion of air slightly above a surface of the disk 12. The flying height of the read/write head over the disk surface is typically less than a micron.
An arm electronics module 30 may include circuits that switch the head function between read and write operations and write drivers for supplying write current to the head 14 during write operations. The write current alters magnetic domains within the disk 12 to store data thereon. The arm electronics module 30 may also include a preamplifier electrically connected to the head 14 by flexible conductive leads 32. During read operations the preamplifier amplifies the read signals produced by the head 14 to increase the read signal amplitude prior to recovering the data bits represented by the read signal. In the write mode the preamplifier scales up the relatively low voltage levels representing the data bits to be written to the disk to a voltage range between about +/−6V and +/−10V. The preamplifier also shapes the write signal waveform to optimize the data writing process.
The configuration and components of the electronics module 30 may vary according to the disk drive design, as will be understood by persons familiar with such technology. Although the module 30 may be mounted anywhere in the disk drive 10, a location proximate the head 14 minimizes signal losses and induced noise in the head signals during a read operation. A preferred mounting location for the module 30 comprises a side surface of the structural arm 18 as shown in FIG. 1.
As shown in FIG. 2, the disk 12 comprises a substrate 50 and a thin film 52, disposed thereover. During write operations current through a write head 14A alters magnetic domains of ferromagnetic material in the thin film 52 for storing the data bits as magnetic transitions. During read operations a read head 14B senses the magnetic transitions to determine the data bits stored on the disk 12.
Data storage media of alternative data storage systems comprise a floppy magnetic disk, a magnetic tape and a magneto-optic disk (not shown in the Figures) cooperating with the head 14 to read and write data to the storage media.
The disk drive read head 14B comprises either a magneto-resistive (MR) sensor or an inductive sensor. The former produces a higher magnitude output signal in response to the magnetic transitions, and thus the output signal exhibits a greater signal-to-noise ratio than an output signal produced by the inductive sensor. The MR sensor is thus preferred, especially when a higher areal data storage density in the disk drive 10 is desired.
A DC (direct current) bias voltage of about 0.04V to 0.2V is supplied by the preamplifier to the read head terminals 54A and 54B via the conductive leads 32 for biasing the read head 14B. Magnetic domains in the thin film 52 passing under the read head 14B alter a resistance of the magneto-resistive material, imposing an AC (alternating current) component on the DC bias voltage, wherein the AC component represents the read data bits. The AC component is detected in the preamplifier, but has a relatively small magnitude (e.g., several millivolts) with respect to the DC bias voltage.
The output signal from the read head 14B, representing data bits read from the disk drive 10 and having an amplitude in a range of several millivolts, is input to a signal processing stage 102 followed by an output or converter stage 104. Typically, both the signal processing stage 102 and the output stage 104 are elements of the preamplifier. The signal processing stage amplifies the signal and supplies the read head bias voltage. The output stage 104 scales up the head signal voltage to a peak voltage value in a range of several hundred millivolts, supplying the scaled-up signal to channel circuits of a channel chip 106 through an interconnect 108. The channel chip 106 detects the read data bits from the voltage pulses, while applying error detection and correction processes to the read data bits.
Desktop computers typically derive their operating power from an AC power source such as a power grid, and can therefore supply continuously high current levels up to the current capacity of the computer power supply. Although it is advantageous to limit the current drawn (power dissipated) by a desktop computer to limit heat build-up within the computer, generally the current supplied to the computer components is not constrained by the ability of the power source to supply the demanded current.
In contrast to a desktop computer, minimizing power dissipation is a crucial design objective for mobile and portable computing devices and data processing systems, for stored music players and for other battery-powered devices that include a mass data storage system operative with a preamplifier. Early designs of mobile computing devices mimizied power dissipation by trading power consumption with operating speed. That is, the operating speed was limited to reduce current consumption and thus extend battery life. Given the continuing demand for higher operating speeds and data rates, such a trade-off is less desirable.
FIG. 3 illustrates a conventional prior art converter or output stage 104 for scaling up and buffering a differential input signal to drive the interconnect 108 to the channel chip 106. The output stage 104 comprises a differential amplifier 110 (further comprising bipolar junction transistors Q7 and Q6) and an output buffer 112 (further comprising bipolar junction transistors Q12 and Q9 each connected as an emitter follower).
The bipolar junction transistors Q6 and Q7 form a differential amplifier with a degeneration resistor R20 connected between an emitter E of the bipolar junction transistor Q6 and an emitter E of the bipolar junction transistor Q7. The degeneration resistor linearizes the amplification and stabilizes the gain of the differential amplifier 110. Collector load resistors R17 and R19 of Q7 and Q6, respectively, are connected to a supply voltage VCC. Current sources 115 and 116 supply current to the respective transistors Q7 and Q6
The emitter followers Q12 and Q9 of the output buffer 112 operate with a fixed bias (6 mA each in one embodiment) supplied by respective current sources 117 and 118. The emitter followers Q12 and Q9 operate as approximately unity gain class-A amplifiers, i.e., current flows in the output circuit of each transistor Q12 and Q9 at all times. The bipolar junction transistors Q9 and Q12 buffer the collector load resistors R17 and R19 of Q7 and Q6, respectively, to drive the interconnect 108 from a low impedance source, thereby maintaining a wide operating bandwidth, typically up to about 700 MHz.
As is known in the art, in one embodiment the current sources 115, 116, 117 and 118 comprise scaled current mirrors implemented as matched area-ratioed bipolar junction transistors and scaled emitter resistors. For exemplary current sources, see the commonly owned patent application entitled, Current Mirrors Having Fast Turn-on Time, filed on May 27, 2005, and assigned application Ser. No. 11/140,269.
The combination of the high data rate and a length of the interconnect 108 between the output stage 104 and the channel chip 106 (typically about two inches) requires consideration of transmission line effects on the interconnect 108. To reduce reflections between the converter stage 104 (conventionally disposed within the preamplifier) and the separate channel chip 106, impedance matching elements Routp 130 and Routn 132 match the preamplifier output impedance to a characteristic impedance of the interconnect 108. In one embodiment, the impedance matching elements Routp 130 and Routn 132 are disposed internal to the preamplifier and thus are elements of the output stage 104, with the output terminals RDP and RDN connected to the interconnect 108.
An impedance matching element (also referred to as a load element) Rterm 134 (having an impedance approximately equal to the characteristic impedance of the interconnect 108) is located at an input side of the channel chip 106 to reduce signal reflections from the channel chip input back through the interconnect 108. In certain applications a characteristic impedance of the interconnect 108 is about 110 ohms and the value of the element Rterm 134 is about 110 ohms.
The output stage 104 operates as follows. The references to more or less current in the operating description are referenced to an idle input condition where VinP−VinN=0. A differential input signal provided on input terminals VinN and VinP from the signal processing stage 102 biases the base of each bipolar junction transistor Q6 and Q7. For a positive input condition VinP−VinN>0 applied to the differential amplifier 110, the bipolar junction transistor Q6 carries more current than in the idle condition (the transistor pulls up or its operating condition moves in a direction of a saturation condition). A voltage at the collector C of Q6 moves toward ground and drives the base B of Q12 toward ground. This condition causes Q12 to carry less current. The input signal supplied to the base B of the bipolar junction transistor Q7 causes it to carry less current than in the idle condition. A voltage at the collector C of Q7 moves toward the supply voltage VCC and drives the base of Q9 toward VCC. Q9 thus carries more current than in the idle condition. Since the current supplied by each of the current sources 117 and 118 is fixed, the decreased current through Q12 and the increased current through Q9 causes the load current ILoad through Rterm 134 to increase. In response to these current conditions, the voltage at the terminal RDP moves in a positive direction and the voltage at the terminal RDN moves in a negative direction with respect to their idle conditions, producing a more positive voltage drop across Rterm 134.
For a negative input condition VinP−VinN<0, the state of the transistors Q6 and Q7 is reversed from the positive input condition. Thus the bipolar junction transistor Q12 carries more current and Q9 carries less current than when in their idle condition. The voltage at the terminal RDP moves in a negative direction (i.e., lower than the RDP voltage for the positive input condition) and the voltage at the terminal RDN moves in a positive direction (greater than the RDN voltage for the positive input condition), producing a voltage drop across Rterm 134 that is less positive or lower than for the positive input condition.
The bias current produced by the current sources 117 and 118 is fixed (i.e., independent of any signal amplitude variations in the output stage 104) and the net current flowing in the bipolar junction transistors Q9 and Q12 is therefore fixed.
From FIG. 3 it can be seen that,iQ9=I118+ILoadiQ12=I117−ILoadwhere iQ9 is the current through the bipolar junction transistor Q9, I118 is the current supplied by current source 118, iQ12 is the current through the bipolar junction transistor Q12, I117 is the current supplied by current source 117 and ILoad is the current through the load resistor Rterm 134.
To maintain operation of the output stage 104 in a linear flow distortion) region and maintain a desired signal bandwidth, both Q9 and Q12 require a minimum or overhead current of Iovrhd. Therefore it is necessary thatI117≧Iovrhd+ILoad max   (1)I118≧Iovrhd+ILoad max   (2)where ILoad max is the maximum load current generated in response to a maximum peak-to-peak input signal for VinP and VinN. Sizing the constant current sources 117 and 118 to satisfy equations (1) and (2), as disclosed in the prior art, ensures that Q9 and Q12 have sufficient current flow to operate in the linear region over the full differential input signal range, which is 400 mVp-p according to one application of the output stage 104. However, sizing both of the current sources 117 and 118 to always supply the maximum current required for all input conditions results in supplying more current than may be needed.
According to industry conventions, it is desired that a total harmonic distortion (THD) introduced by the output stage 104 be less than about 0.5% for a 400 mVp-p output swing at the output terminals RDN and RDP.
When operating in a disk drive data storage system for desktop computer with unlimited current capacity, the current sources 117 and 118 are designed to supply a constant current of about 6 mA, an amount sufficient to satisfy the maximum input signal conditions and current overhead requirements discussed above and the THD requirement.
For a disk drive data storage system operative with a mobile or portable computing device, typically deriving its power from an on-board battery, it is desired to improve the power efficiency of the output stage 104 to conserve battery life. However, the THD requirements must be satisfied and proper output stage performance maintained.